This application claims the priority of Korean Patent Application No. 2004-22025, filed on Mar. 31, 2004, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor including square type storage nodes for securing the capacitance of capacitors while reducing a cell size and a method of manufacturing the same.
2. Description of the Related Art
As the technology of manufacturing a semiconductor device improves, the size of transistors is reduced and the integration of a semiconductor device is rapidly increased. The reduction of a chip size is important to develop a high integration memory semiconductor device. In the case of a dynamic random access memory (DRAM) device, the device is highly integrated like 1 gigabits (G), 4 G, 8 G. Thus, chip size must be reduced. For example, new cell structures, such as 7F2, 6F2, and 4F2 structures, that are derived from an 8F2 structure are provided to reduce the chip size. Such cell structures are known for reducing the chip size even when applied to a minimum line width F, which is the same as that of the 8F2 cell structure.
On the other hand, the data retention characteristic, in other words, the refresh characteristic is recognized as an important factor in determining the stable operation characteristic of a device. Examples of the factors for determining the refresh characteristic include the capacitance of a cell capacitor, a bit line loading capacitance, and various cell leakage currents generated in connection with a storage node. The absolute amount of charges stored in a cell capacitor of a DRAM device is reduced over time because various leakage currents are generated. Thus, the previously stored information is refreshed within a predetermined time interval. Here, the above-described factors play important roles in determining the refreshing time interval.
Thus, it is important to secure the capacitance of a stable capacitor in order to secure a data storage characteristic even when such a new cell structure is used. In order to increase the capacitance of the cell capacitor, the dielectric layer of the capacitor must be formed of a material having a high dielectric constant or the effective area of the capacitor must be increased.
In order to increase the effective area of the capacitor, the area and the stack height of a unit cell capacitor are increased. However, the increase of the stack of the capacitor in a capacitor over bit line (COB) structure has a limit, because the stack may fall down. Thus, the area occupied by the capacitors should be previously secured in order to increase the effective area of the capacitor.
However, it is known that the area occupied by capacitors in such a new cell structure is reduced from the area in the 8F2 cell structure by more than 50%. Thus, the secure of the capacitance of the capacitor becomes a precondition of adopting such a new cell structure.
FIG. 1 is a plan view illustrating a conventional DRAM semiconductor device of 6F2 structure.
Referring to FIG. 1, in a diagonal array type structure of conventional 6F2 cell structures, one memory cell is formed at the crossing point of word line 20 and bit line 50 that are perpendicular to each other. In addition, the major axis of an active region 11, defined by a device isolation region 15, is arranged in a direction diagonal to the word line 20 and the bit line 50.
In this case, the distance between the word lines 20 is twice the minimum pitch or minimum line width F, and the distance between the bit lines 50 is three times the minimum pitch F. Accordingly, the cell size of the 6F2 structure is smaller than the cell size of the 8F2 structure.
However, storage nodes 80 are formed on the bit lines 50 to form capacitors of the COB structure, in order to realize a DRAM cell, as shown in FIG. 1. The storage nodes 80 are electrically connected to first contact pads 41 that are preliminarily arranged to electrically connect the active regions 11 between the word lines 20, by interconnections such as storage contacts.
In order to smoothly connect the storage nodes 80 to the active regions 11, the storage nodes 80 overlap the first contact pads 41 and the storage contacts overlap the first contact pads 41. Six storage nodes 80 are arranged to form a hexagon due to the arrangement of the active region 11, and the storage node 80 is not formed on an area A at the center of the storage nodes 80 array, which form a hexagon.
Such an empty area A exists at a location of a second contact pad 45 where the bit line 50 and a bit line connect contact of electrically connecting the active region 11 overlap. The empty area A reduces the area of the storage nodes 80. Accordingly, the area to be occupied by the storage nodes 80 is reduced in a unit cell area.
For example, in the case of a device in which storage nodes 80 are formed as a one cylindrical stack (OCS) structure while having a design rule of 80 nm, a separation distance of at least 60 nm should be secured between the storage nodes 80, in order to prevent an electrode fall-down phenomenon or a bridge phenomenon between adjacent storage nodes 80.
When considering the separation distance of 60 nm, the pitch of the storage node 80 becomes 2F, in other words, about 160 nm. Thus the diameter of the area occupied by the storage nodes 80 becomes about 100 nm. Since the area occupied by the storage nodes 80 is small, the stack height of the storage nodes 80 is limited. Actually, it is difficult to form the storage nodes 80 in a cylinder shape within such an area. Thus, it is difficult to improve the capacitance of the capacitors using such storage nodes 80.
In order to practically use the new cell structure as 6F2 in a memory semiconductor device like DRAM, it is required to increase an area occupied by storage nodes 80. Even when Ta2O5 or Al2O3 is used instead of a conventional NO dielectric layer, the effective area of the capacitors should be increased to secure the capacitance of the cell capacitors, because the dielectric constant of such a dielectric material is similar to conventional dielectric material. As a result, the area of the storage nodes 80 must be increased.